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Taheri, MohammadReza, Shafiee, Nasim, Esmaeildoust, Mohammad, Amirjamshidi, Zhale, Sabbaghi-nadooshan, Reza, Navi, Keivan. (1393). A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set. , 2(1), 43-54.
MohammadReza Taheri; Nasim Shafiee; Mohammad Esmaeildoust; Zhale Amirjamshidi; Reza Sabbaghi-nadooshan; Keivan Navi. "A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set". , 2, 1, 1393, 43-54.
Taheri, MohammadReza, Shafiee, Nasim, Esmaeildoust, Mohammad, Amirjamshidi, Zhale, Sabbaghi-nadooshan, Reza, Navi, Keivan. (1393). 'A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set', , 2(1), pp. 43-54.
Taheri, MohammadReza, Shafiee, Nasim, Esmaeildoust, Mohammad, Amirjamshidi, Zhale, Sabbaghi-nadooshan, Reza, Navi, Keivan. A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set. , 1393; 2(1): 43-54.

A High Speed Residue-to-Binary Converter for Balanced 4-Moduli Set

Journal of Computing and Security
مقاله 4، دوره 2، شماره 1، فروردین 2015، صفحه 43-54    اصل مقاله (1.1 M)
نویسندگان
MohammadReza Taheri1؛ Nasim Shafiee1؛ Mohammad Esmaeildoust2؛ Zhale Amirjamshidi3؛ Reza Sabbaghi-nadooshan3؛ Keivan Navi* 1
1Faculty of Computer Science and Engineering, Shahid Beheshti University, GC, Tehran, Iran
2Faculty of Marine Engineering, Khorramshahr University of Marine Science and Technology, Khuzestan, Iran
3Electronic Engineering Department, Islamic Azad University, Central Tehran Branch, Tehran, Iran
چکیده
The moduli set 2 n−1 − 1, 2 n+1 − 1, 2 n , 2 n − 1 has been recently proposed inliterature for class of 4n-bit dynamic range in residue number system. Due toonly utilizing modulus in the form of 2 k − 1 besides modulo 2 n , this moduliset enjoys the efficient Arithmetic Unit (AU) in its architecture. Not only doesthe efficiency of a RNS system depend on the residue arithmetic unit but italso is limited to the residue to binary converter. In this paper, a new two levelresidue-to-binary converter architecture based on Mixed Radix Conversion(MRC) is presented for the aforementioned moduli set. The proposed converterincludes two levels of design based on MRC properties. Firstly, the 3-modulisubset 2 n−1 − 1, 2 n+1 − 1, 2 n − 1 is properly organized and as it does notcalculate several values, it results in some cost modifications. Eventually, atwo-moduli set 2 n−1 − 1 2 n+1 − 1 (2 n − 1) , 2 n is formed to compute thebinary of RNS counterpart. The proposed architecture is shown to be moreefficient both in terms of hardware cost and conversion delay in comparisonwith the related state-of-the-art works.
کلیدواژه‌ها
Mixed Radix Conversion؛ Residue Arithmetic؛ Residue Number System؛ Residue-to-Binary Converter
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